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cy14b101q1 cy14b101q2 cy14b101q3 1-mbit (128 k 8) serial spi nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50091 rev. *l revised may 24, 2013 1-mbit (128 k 8) serial spi nvsram features 1-mbit nonvolatile static random access memory (nvsram) ? internally organized as 128 k 8 ? store to quantumtrap nonvolatile elements initiated automatically on power-down (autostore) or by user using hsb pin (hardware store) or spi instruction (software store) ? recall to sram initiated on power-up (power-up recall) or by spi instruction (software recall) ? automatic store on power-down with a small capacitor (except for cy14b101q1) high reliability ? infinite read, write, and recall cycles ? 1 million store cycles to quantumtrap ? data retention: 20 years high speed serial peripheral interface (spi) ? 40 mhz clock rate ? supports spi mode 0 (0,0) and mode 3 (1,1) write protection ? hardware protection using write protect (wp ) pin ? software protection using write disable instruction ? software block protection for 1/4,1/2, or entire array low power consumption ? single 3 v +20%, ?10% operation ? average active current of 10 ma at 40 mhz operation industry standard configurations ? industrial temperature ? cy14b101q1 has identical pin configuration to industry standard 8-pin nv memory ? 8-pin dual flat no-lead (dfn) package and 16-pin small outline integrated circuit (soic) package ? restriction of hazardous s ubstances (rohs) compliant functional overview the cypress cy14b101q1/cy14b101q2/cy14b101q3 combines a 1-mbit nvsram with a nonvolatile element in each memory cell with serial spi in terface. the memory is organized as 128 k words of 8 bits each. the embedded nonvolatile elements incorporate the quantumtrap technology, creating the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while the quantumtrap cell provides highly reliable nonvolatile storage of data. data transfers from sram to the nonvolatile elements (store operation) takes place automatically at power-down (except for cy14b101q1). on power-up, data is restored to the sram from the nonvolatile memory (recall operation). both store and recall operations can also be initiated by the user through spi instruction. configuration feature cy14b101q1 cy14b101q2 cy14b101q3 autostore no yes yes software store yes yes yes hardware store no no yes instruction register address decoder data i/o register status register power control store/recall control instruction decode write protect control logic quantumtrap store recall si sck v cc v cap so hsb 128 k x 8 sram array 128 k x 8 a0-a16 d0-d7 hold cs wp logic block diagram not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 2 of 27 contents pinouts .............................................................................. 3 pin definitions .................................................................. 4 device operation .............................................................. 5 sram write ................................................................. 5 sram read ................................................................ 5 store operation ....................................................... 5 autostore operation .................................................... 6 software store operation ........................................ 6 hardware store and hsb pin operation ................. 6 hardware recall (power-up) .................................. 6 software recall ....................................................... 6 disabling and enabling autostore ............................... 7 serial peripheral interface ............................................... 7 spi overview ............................................................... 7 spi modes ................................................................... 8 spi operating features .................................................... 9 power-up .................................................................... 9 power-on reset .......................................................... 9 power-down ................................................................ 9 active power and standby power modes ................... 9 spi functional description .... ................................. ......... 9 status register ............................................................... 10 read status register (rdsr) instruction ................. 10 write status register (wrsr) instruction ................ 10 write protection and block protection ......................... 11 write enable (wren) instruction .............................. 11 write disable (wrdi) instruction .............................. 11 block protection ........................................................ 11 write protect (wp) pin .............................................. 12 memory access .............................................................. 12 read sequence (read) instruction .......................... 12 write sequence (write) instru ction ............ ............ 12 software store (store) instruction ...................... 13 software recall (recall) instruction .................. 14 autostore enable (asenb) in struction .... ............ ..... 14 autostore disable (asdisb) instruction ................... 14 hold pin operation ................................................. 14 maximum ratings ........................................................... 15 operating range ............................................................. 15 dc electrical characteristics ........................................ 15 data retention and endurance ..................................... 16 capacitance .................................................................... 16 thermal resistance ........................................................ 16 ac test loads and waveforms ..................................... 16 ac test conditions ........................................................ 16 ac switching characteristics ....................................... 17 switching waveforms .................................................... 17 autostore or power-up recall .................................. 18 software controlled store and recall cycles ...... 19 switching waveforms .................................................... 19 hardware store cycle ................................................. 20 switching waveforms .................................................... 20 ordering information ...................................................... 21 ordering code definitions ..... .................................... 21 package diagrams .......................................................... 22 acronyms ........................................................................ 24 document conventions ................................................. 24 units of measure ....................................................... 24 document history page ................................................. 25 sales, solutions, and legal information ...................... 27 worldwide sales and design s upport ......... .............. 27 products .................................................................... 27 psoc solutions ......................................................... 27 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 3 of 27 pinouts figure 1. 8-pin dfn pinout [1, 2, 3] figure 2. 16-pin soic pinout pad 1 4 2 3 8 5 7 6 si v cc sck so cs wp cy14b101q1 top view ( not to scale ) v ss pad 1 4 2 3 8 5 7 6 si v cc sck hold so cs v cap cy14b101q2 top view (not to scale) hold exposed exposed o o v ss nc wp v cap 1 2 3 4 5 6 7 8 9 10 11 12 13 nc 16 15 14 v cc so si sck cs hsb nc nc nc hold nc cy14b101q3 top view not to scale v ss notes 1. hsb pin is not available in 8-pin dfn packages. 2. cy14b101q1 part does not have v cap pin and does not support autostore. 3. cy14b101q2 part does not have wp pin. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 4 of 27 pin definitions pin name i/o type description cs input chip select. activates the device when pulled low. driving this pin high puts the device in low power standby mode. sck input serial clock. runs at speeds up to maximum of f sck . serial input is latched at the rising edge of this clock. serial output is driven at the falling edge of the clock. si input serial input. pin for input of all spi instructions and data. so output serial output. pin for output of data through spi. wp input write protect. implements hardware write protection in spi. hold input hold pin. suspends serial operation. hsb input/output output: indicates busy status of nvsram when low. after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keeps this pin high (external pull-up resistor connection optional). input: hardware store implemented by pulling this pin low externally. v cap power supply autostore capacitor. suppl ies power to the nvsram during power loss to store data from the sram to nonvolatile elements. if autostore is not needed, this pin must be left as no connect. it must never be connected to v ss . nc no connect no connect: this pin is not connected to the die. v ss power supply ground v cc power supply power supply (2.7 v to 3.6 v) exposed pad no connect the exposed pad on the bottom of 8-pin dfn package is not connected to the die. it is recommended to connect the exposed pad to v ss . thermal vias can be used to increase thermal conductivity. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 5 of 27 device operation cy14b101q1/cy14b101q2/cy14b1 01q3 is a 1-mbit nvsram memory with a nonvolatile element in each memory cell. all the reads and writes to nvsram happen to the sram, which gives nvsram the unique capability to handle infinite writes to the memory. the data in sram is secured by a store sequence, which transfers the data in parallel to the nonvolatile quantumtrap cells. a small capacitor (v cap ) is used to autostore the sram data in nonvolatile cells when power goes down providing power-down data security. the quantumtrap nonvolatile elements built in the reliable sonos technology make nvsram the ideal choice for secure data storage. the 1 mbit memory array is organized as 128 k words 8 bits. the memory is accessed through a standard spi interface that enables very high clock speeds up to 40 mhz with zero cycle delay read and write cycles. this device supports spi modes 0 and 3 (cpol, cpha = 0, 0 and 1, 1) and operates as spi slave. the device is enabled using the chip select ( cs ) pin and accessed through serial input (si), serial output (so), and serial clock (sck) pins. this device provides the feature for hardware and software write protection through the wp pin and wrdi instruction respectively along with mechanisms for block wr ite protection (1/4, 1/2, or full array) using bp0 and bp1 pins in the status register. further, the hold pin can be used to suspend any serial communication without resetting the serial sequence. cy14b101q1/cy14b101q2/cy14 b101q3 uses the standard spi opcodes for memory access. in addition to the general spi instructions for read and write, it provides four special instructions which enable acce ss to four nvsram specific functions: store, recall, autostore disable (asdisb), and autostore enable (asenb). the major benefit of serial ( spi) nvsram over serial eeproms is that all reads and writes to nvsram are performed at the speed of spi bus with zero cycle delay. ther efore, no wait time is required after any of the memory accesses. the store and recall operations need finite time to complete and all memory accesses are inhibited during this time. while a store or recall operation is in progress, the busy status of the device is indicated by the hardware store busy (hsb ) pin and also reflected on the rdy bit of the status register. the device is available in three different pin configurations that enable the user to choose a part which fits in best in their application . the feature summary is given in table 1 . sram write all writes to nvsram are carried out on the sram and do not use up any endurance cycles of the nonvolatile memory. this enables the user to perform infinite write operations. a write cycle is performed through the write instruction. the write instruction is issued through the si pin of the nvsram and consists of the write opcode, three bytes of address, and one byte of data. write to nvsram is done at spi bus speed with zero cycle delay. the device allows burst mode writes to be performed through spi. this enables write operati ons on consecutive addresses without issuing a new write inst ruction. when the last address in memory is reached in burst mode, the address rolls over to 0x0000 and the device continues to write. the spi write cycle sequence is defined in the memory access section of spi protocol description. sram read a read cycle is performed at th e spi bus speed and the data is read out with zero cycle delay after the read instruction is executed. the read instruction is issued through the si pin of the nvsram and consists of the read opcode and 3 bytes of address. the data is read out on the so pin. this device allows burst mode reads to be performed through spi. this enables reads on consecutive addresses without issuing a new read instruction. when the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read. the spi read cycle sequence is defined in the memory access section of spi protocol description. store operation store operation transfers the data from the sram to the nonvolatile quantumtrap cells. th e device stores data to the nonvolatile cells using one of the three store operations: autostore, activated on device power-down; software store, activated by a store instruction; and hardware store, activated by the hsb . during the store cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile el ements. after a store cycle is initiated, read/write to cy14b101q1/cy14b101q2/cy14b101q3 is inhibited until the cycle is completed. the hsb signal or the rdy bit in the status register can be monitored by the system to detect if a store or software recall cycle is in progress. the busy status of nvsram is indicated by hsb being pulled low or rdy bit being set to ?1?. to avoid unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. however, softwa re initiated store cycles are performed regardless of whether a write operation has taken place. table 1. feature summary feature cy14b101q1 cy14b101q2 cy14b101q3 wp yes no yes v cap no yes yes hsb no no yes autostore no yes yes power up recall yes yes yes hardware store no no yes software store yes yes yes not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 6 of 27 autostore operation the autostore operation is a unique feature of nvsram, which automatically stores the sram data to quantumtrap during power-down. this store makes use of an external capacitor (v cap ) and enables the device to safely store the data in the nonvolatile memory when power goes down. during normal operation, the device draws current from v cc to charge the capacitor connected to the v cap pin. when the voltage on the v cc pin drops below v switch during power-down, the device inhibits all memory accesses to nvsram and automatically performs a conditional store operation using the charge from the v cap capacitor. the autostore operation is not initiated if no write cycle has been performed since the last recall. note if a capacitor is not connected to v cap pin, autostore must be disabled by issuing the autostore disable instruction specified in autostore disable (asdisb) instruction on page 14. if autostore is enabled without a capacitor on the v cap pin, the device attempts an autostore op eration without su fficient charge to complete the store. this corrupts the data stored in the nvsram and status register. to resume normal functionality, the wrsr instruction must be issued to update the nonvolatile bits bp0, bp1 and wpen in the status register. figure 3 shows the proper connectio n of the storage capacitor (v cap ) for autostore operation. see dc electrical characteristics on page 15 for the size of the v cap . note cy14b101q1 does not support autostore operation. the user must perform software store operation by using the spi store instruction to secure the data. figure 3. autostore mode software store operation software store enables the user to trigger a store operation through a special spi instruction. store operation is initiated by executing store instruction irrespective of whether a write has been performed since the last nv operation. a store cycle takes t store time to complete, during which all the memory accesses to nvsram are inhibited. the rdy bit of the status register or the hsb pin may be polled to find the ready or busy status of the nvsram. after the t store cycle time is completed, the sram is activated again for read and write operations. hardware store and hsb pin operation the hsb pin in cy14b101q3 is used to control and acknowledge store operations. if no store or recall is in progress, this pin can be used to request a hardware store cycle. when the hsb pin is driven low, nvsram conditionally initiates a store operation after t delay duration. an actual store cycle starts only if a write to the sram has been performed since the last stor e or recall cycle. reads and writes to the memory are inhibited for t store duration or as long as hsb pin is low. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by an internal 100 k ? pull-up resistor. note for successful last data byte store, a hardware store should be initiated atle ast one clock cycle after the last data bit d0 is received. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. the hsb pin must be left unconnected if not used. note cy14b101q1/cy14b101q2 do not have hsb pin. rdy bit of the spi status register may be probed to determine the ready or busy status of nvsram. recall operation a recall operation transfers th e data stored in the nonvolatile quantumtrap elements to the sram. a recall may be initiated in two ways: hardware recall, initiated on power-up; and software recall, initiated by a spi recall instruction. internally, recall is a two-step procedure. first, the sram data is cleared. next, the nonvolatile information is transferred into the sram cells. all memory accesses are inhibited while a recall cycle is in progress. the recall operation does not alter the data in the nonvolatile elements. hardware recall (power-up) during power-up, when v cc crosses v switch , an automatic recall sequence is initiated which transfers the content of nonvolatile memory on to the sram. the data would previously have been stored on the nonvolatile memory through a store sequence. a power-up recall cycle takes t fa time to complete and the memory access is disabled during this time. hsb pin is used to detect the ready status of the device. software recall software recall enables the user to initiate a recall operation to restore t he content of nonvolatile memory on to the sram. a software recall is issued by using the spi instruction for recall. a software recall takes t recall time to complete during which all memory accesses to nvsram are inhibited. the controller must provide sufficient delay for the recall operation to complete before issuing any memory access instructions. 0.1 uf v cc 10 kohm v cap cs v cap v ss v cc not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 7 of 27 disabling and enabling autostore if the application does not requir e the autostore fe ature, it can be disabled by using the asdisb instruction. if this is done, the nvsram does not perform a store operation at power-down. autostore can be re-enabled by using the asenb instruction. however, these operations are not nonvolatile and if the user need this setting to survive the power cycle, a store operation must be performed following autostore disable or enable operation. note cy14b101q2/cy14b101q3 has autostore enabled from the factory and cy14b101q1/cy14b101q2/cy14b101q3 comes from the factory with 0x00 written in all cells. in cy14b101q1, v cap pin is not present and autostore option is not available. the autostore enable and disable instructions to cy14b101q1 are ignored. note if autostore is disabled and v cap is not required, then the v cap pin must be left open. v cap pin must never be connected to ground. power-up recall operation cannot be disabled in any case. serial peripheral interface spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), and serial clock (sck) pins. cy14b101q1/cy14b101q2/cy14b101q3 provides serial access to nvsram through spi interface. the spi bus on this device can run at speeds up to 40 mhz. the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on spi bus is activated using a cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both these modes, data is clocke d into the nvsram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated the first byte transferred from the bus master is the opcode. following the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can be issued. the commonly used terms used in spi protocol are as follows: spi master the spi master device controls the operations on a spi bus. a spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of the slave devices using the cs pin. all the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchronized with this clock. spi slave the spi slave device is activate d by the master through the chip select line. a slave device gets the sck as an input from the spi master and all the communicat ion is synchronized with this clock. spi slave neve r initiates a communication on the spi bus and acts on the instruction from the master. cy14b101q1/cy14b101q2/cy14b101q3 operates as a spi slave and may share the spi bus with other spi slave devices. chip select (cs ) for selecting any slave device, the master needs to pull-down the corresponding cs pin. any instructio n can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) serial clock is generated by the spi master and the communication is synchronized with this clock after cs goes low. cy14b101q1/cy14b101q2/cy14b101q3 enables spi modes 0 and 3 for data communication. in both these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefore, the first rising edge of sck signifies the arrival of the first bit (msb) of spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck. data transmission - si and so spi data bus consists of two lines, si and so, for serial data communication. the si is also re ferred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the master issues instructions to the slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. most signific ant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 1 mbit serial nvsram requires a 3-byte address for any read or write operation. however, si nce the actual address is only 17 bits, it implies that the first seven bits which are fed in are ignored by the device. although these seven bits are ?don?t care?, cypress recommends that these bi ts are treated as 0s to enable seamless transition to higher memory densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. cy14b101q1/cy14b101q2/cy14b101q3 uses the standard opcodes for memory accesses. in addition to the memory accesses, it provides additional opcodes for the nvsram specific functions: store, recall, autostore enable, and autostore disable. see table 2 on page 9 for details. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 8 of 27 invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin till the next falling edge of cs and the so pin remains tristated. status register cy14b101q1/cy14b101q2/cy14b101q3 has an 8-bit status register. the bits in the status register are used to configure the spi bus. these bits are described in the ta b l e 4 on page 10. spi modes cy14b101q1/cy14b101q2/cy14b101q3 may be driven by a microcontroller with its spi periph eral running in either of the following two modes: spi mode 0 (cpol=0, cpha=0) spi mode 3 (cpol=1, cpha=1) for both these modes, the input da ta is latched-in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge, after the clock toggles, is considered. the output data is available on the falling edge of sck. the two spi modes are shown in figure 5 and figure 6 . the status of clock when the bus mast er is in standby mode and not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 cpol and cpha bits must be set in the spi controller for the either mode 0 or mode 3. the device detects the spi mode from the status of sck pin when the device is selected by bringing the cs pin low. if sck pin is low when the device is selected, spi mode 0 is assumed and if sck pin is high, it works in spi mode 3. figure 4. system configuration using spi nvsram xq101b41yc xq101b41yc ucontroller sck mosi miso si so o sis kc ss c k cs hold hold cs cs1 cs2 hold1 hold2 figure 5. spi mode 0 figure 6. spi mode 3 lsb msb 765432 10 cs sck si 0 1 2 3 4 5 6 7 cs sck si 765432 10 s s 0 1 2 3 4 5 6 7 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 9 of 27 spi operating features power-up power-up is defined as the condition when the power supply is turned on and v cc crosses v switch voltage. during this time, the cs must be allowed to follow the v cc voltage. therefore, cs must be connected to v cc through a suitable pull-up resistor. as a built-in safety feature, cs is both edge sensitive and level sensitive. after power-up, the device is not selected until a falling edge is detected on cs . this ensures that cs is high, before going low to start the first operation. as described earlier, nvsram performs a power-up recall operation after power-up and therefore, all memory accesses are disabled for t fa duration after power-up. the hsb pin can be probed to check the ready or busy status of nvsram after power-up. power-on reset a power-on reset (por) circuit is included to prevent inadvertent writes. at power-up, the device does not respond to any instruction until the v cc reaches the por threshold voltage (v switch ). after v cc transitions the por threshold, the device is internally reset and performs an power-up recall operation. during power-up recall all device accesses are inhibited. the device is in the following state after por: deselected (after power-up, a falling edge is required on cs before any instructio ns are started). standby power mode not in the hold condition status register state: ? write enable (wen) bit is reset to 0. ? wpen, bp1, bp0 unchanged from previous store operation ? don?t care bits 4-6 are reset to 0. the wpen, bp1, and bp0 bits of the status register are nonvolatile bits and remain unchanged from the previous store operation. before selecting and issuing instructions to the memory, a valid and stable v cc voltage must be applied. this voltage must remain valid until the end of the instruction transmission. power-down at power-down (continuous decay of v cc ), when v cc drops from the normal operating voltage and below the v switch threshold voltage, the device stops responding to any instruction sent to it. if a write cycle is in progress and the last data bit d0 has been received when the power goes down, it is allowed t delay time to complete the write. after which all memory accesses are inhibited and a conditional autostore operation is performed (autostore is not performed if no writes have happened since last recall cycle). this featur e prevents inadvertent writes to nvsram from happening during power-down. however, to completely avoid the possibility of inadvertent writes during power-down, ensure that the device is deselected and is in standby power mode, and the cs follows the voltage applied on v cc . active power and standby power modes when cs is low, the device is selected, and is in the active power mode. the device consumes i cc current, as specified in dc electrical characteristics on page 15. when cs is high, the device is deselected and the device goes into the standby power mode if a store or recall cycl e is not in progress. if a store or recall cycle is in pr ogress, the device goes into the standby power mode after the store or recall cycle is completed. in the standby power mode, the current drawn by the device drops to i sb . spi functional description the cy14b101q1/cy14b101q2/cy14b101q3 uses an 8-bit instruction register. instructions and their operation codes are listed in ta b l e 2 . all instructions, addresses, and data are transferred with the msb first and start with a high to low cs transition. there are, in all, 10 spi instructions which provide access to most of the functions in nvsram. further, the wp , hold and hsb pins provide additional functionality driven through hardware. the spi instructions are divided based on their functionality in the following types: ? status register access: rds r and wrsr instructions ? write protection functions: wr en and wrdi instructions along with wp pin and wen, bp0, and bp1 bits ? sram memory access: read and write instructions ? nvsram special instructions: store, recall, asenb, and asdisb table 2. instruction set instruction category instruction name opcode operation status register control instruc- tions wren 0000 0110 set write enable latch wrdi 0000 0100 reset write enable latch rdsr 0000 0101 read status register wrsr 0000 0001 write status register sram read/write instructions read 0000 0011 read data from memory array write 0000 0010 write data to memory array special nv instructions store 0011 1100 software store recall 0110 0000 software recall asenb 0101 1001 autostore enable asdisb 0001 1001 autostore disable reserved - reserved - 0001 1110 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 10 of 27 status register the status register bits are listed in ta b l e 4 . the status register consists of a ready bit (rdy ) and data protection bits bp1, bp0, wen, and wpen. the rdy bit can be polled to check the ready or busy stat us while a nvsram store or software recall cycle is in progress. the status register can be modified by wrsr in struction and read by rdsr instruction. however, only the wpen, bp1, and bp0 bits of the status register can be modified by us ing wrsr instruction. the wrsr instruction has no effect on wen and rdy bits. the default value shipped from the factory for wen, bp0, bp1, bits 4-6 and wpen bits is ?0?. read status register (rdsr) instruction the rdsr instruction provides a ccess to the status register. this instruction is used to prob e the write enable status of the device or the ready status of the device. rdy bit is set by the device to ?1? whenever a store or software recall cycle is in progress. the block protection and wpen bits indicate the extent of protection employed. this instruction is issued after the falling edge of cs using the opcode for rdsr. write status register (wrsr) instruction the wrsr instruction enables the user to write to the status register. however, this instruction cannot be used to modify bit 0 and bit 1 (rdy and wen). the bp0 and bp1 bits can be used to select one of four levels of block protection. further, wpen bit must be set to ?1? to enable the use of writ e protect (wp ) pin. wrsr instruction is a write instruction and needs writes to be enabled (wen bit set to ?1?) using the wren instruction before it is issued. the instruction is issued after the falling edge of cs using the opcode for wrsr followed by 8 bits of data to be stored in the status register. si nce only bits 2, 3, and 7 can be modified by wrsr instruction; therefore, it is recommended to leave the bits 4-6 as ?0? while writing to the status register note in cy14b101q1/cy14b101q2/ cy14b101q3, the values written to status register are saved to nonvolatile memory only after a store operation. if autostore is disabled (or while using cy14b101q1), any modifications to the status register must be secured by performing a software store operation. note cy14b101q2 does not have wp pin. any modification to bit 7 of the status register ha s no effect on the functionality of cy14b101q2. table 3. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen (0) x (0) x (0) x (0) bp1 (0) bp0 (0) wen (0) rdy table 4. status register bit definition bit definition description bit 0 (rdy ) ready read only bit indicates the ready status of device to perform a memory access. this bit is set to ?1? by the device while a store or software recall cycle is in progress. bit 1 (wen) write enable wen indicates if the device is writ e enabled. this bit defaults to ?0? (disabled) on power-up. wen = '1' --> write enabled wen = '0' --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details see table 5 on page 11. bit 3 (bp1) block protect bit ?1? used for block protection. for details see table 5 on page 11. bits 4-6 don?t care bits are writable and vola tile. on power-up, bits are written with ?0?. bit 7 (wpen) write protect enable bit used for ena bling the function of write protect pin (wp ). for details see table 6 on page 12. figure 7. read status regi ster (rdsr) instruction timing cs sck so 01234567 si 0000 01 0 0 1 msb lsb hi-z 012345 67 data lsb d0d1 d2 d3 d4 d5d6 msb d7 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 11 of 27 write protection and block protection cy14b101q1/cy14b101q2/cy1 4b101q3 provides features for both software and hardware write protection using wrdi instruction and wp . additionally, this device also provides block protection mechanism through bp0 and bp1 pins of the status register. the write enable and disable stat us of the device is indicated by wen bit of the status register. the write instructions (wrsr and write) and nvsram special in struction (store, recall, asenb, and asdisb) need the write to be enabled (wen bit = 1) before they can be issued. write enable (wren) instruction on power-up, the device is always in the write disable state. the following write, wrsr, or nvsram special instruction must therefore be preceded by a write enable instruction. if the device is not write enabled (wen = ?0?), it ignores the write instructions and returns to the standby state when cs is brought high. a new cs falling edge is required to re-initiate serial communi- cation. the instruction is issued following the falling edge of cs . when this instruction is used, t he wen bit of status register is set to ?1?. wen bit defaults to ?0? on power-up. note after completion of a write instruction (wrsr or write) or nvsram special instruct ion (store, recall, asenb, and asdisb) instruction, we n bit is cleared to ?0?. this is done to provide protection from any inadvertent writes. therefore, wren instruction must be used before a new write instruction is issued. write disable (wrdi) instruction write disable instruction disables the write by clearing the wen bit to ?0? in order to protect the device against inadvertent writes. this instruction is issued following the falling edge of cs followed by opcode for wrdi instruction. the wen bit is cleared on the rising edge of cs following a wrdi instruction. block protection block protection is provided usi ng the bp0 and bp1 pins of the status register. these bits can be set using wrsr instruction and probed using the rdsr instru ction. the nvsram is divided into four array segments. one-quarter, one-half, or all of the memory segments can be protected. any data within the protected segment is read only. ta b l e 5 shows the function of block protect bits. figure 8. write status regi ster (wrsr) instruction timing cs sck so 0123 4567 si 0000000 1 msb lsb d2 d3 d7 hi-z 012345 67 opcode data in xxx xx figure 9. wren instruction 0 0 0 0 0 1 1 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 figure 10. wrdi instruction table 5. block write protect bits level status register bits array addresses protected bp1 bp0 000 none 1 (1/4) 0 1 0x18000?0x1ffff 2 (1/2) 1 0 0x10000?0x1ffff 3 (all) 1 1 0x00000?0x1ffff 0 0 0 0 0 1 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 12 of 27 write protect (wp ) pin the write protect pin (wp ) is used to provide hardware write protection. wp pin enables all normal read and write operations when held high. when the wp pin is brought low and wpen bit is ?1?, all write operations to the status register are inhibited. the hardware write protection f unction is blocked when the wpen bit is ?0?. this enables the user to install the device in a system with the wp pin tied to ground, and still write to the status register. wp pin can be used along with wpen and block protect bits (bp1 and bp0) of the status regist er to inhibit writes to memory. when wp pin is low and wpen is set to ?1?, any modifications to status register are disabl ed. therefore, the memory is protected by setting the bp0 and bp1 bits and the wp pin inhibits any modification of the status register bits, providing hardware write protection. note wp going low when cs is still low has no effect on any of the ongoing write operatio ns to the status register. note cy14b101q2 does not have wp pin and therefore does not provide hardware write protection. ta b l e 6 summarizes all the protection features of this device. memory access all memory accesses are done using the read and write instructions. these instructions cannot be used while a store or recall cycle is in progress. a store cycle in progress is indicated by the rdy bit of the status register and the hsb pin. read sequence (read) instruction the read operations on this device are performed by giving the instruction on si and reading the output on so pin. the following sequence needs to be followed for a read operation: after the cs line is pulled low to select a device, the read opcode is transmitted through the si line followed by three bytes of address. the most significant address byte contains a16 in bit 0 and other bits as ?don?t cares?. address bits a15 to a0 are sent in the following two address bytes. after the last address bit is transmitted on the si pin, th e data (d7-d0) at the specific address is shifted out on the so line on the falling edge of sck starting with d7. any other data on si line after the last address bit is ignored. cy14b101q1/cy14b101q2/cy14b101q3 allows reads to be performed in bursts through spi, which can be used to read consecutive addresses without issuing a new read instruction. if only one byte is to be read, the cs line must be driven high after one byte of data comes out. however, the read sequence may be continued by holding the cs line low and the address is automatically incremented and data continues to shift out on so pin. when the last data memory address (0x1ffff) is reached, the address rolls over to 0x0000 and the device continues to read. write sequence (write) instruction the write operations on this device are performed through the si pin. to perform a write operation, if the device is write disabled, then the device must first be write enabled through the wren instruction. when the writes are enabled (wen = ?1?), write instruction is issued after the falling edge of cs . a write instruction constitutes transmitting the write opcode on si line followed by 3 bytes of address and the data (d7-d0) which is to be written. the most significant address byte contains a16 in bit 0 with other bits being ?don?t cares?. address bits a15 to a0 are sent in the following two address bytes. cy14b101q1/cy14b101q2/cy14b101q3 enables writes to be performed in bursts through spi, which can be used to write consecutive addresses without issuing a new write instruction. if only one byte is to be written, the cs line must be driven high after the d0 (lsb of data) is transmitted. however, if more bytes are to be written, cs line must be held low and address is incremented automatical ly. the following bytes on the si line are treated as data bytes and written in the successive addresses. when the last data memory address (0x1ffff) is reached, the address rolls over to 0x0000 and the device continues to write. the wen bit is reset to ?0? on completion of a write sequence. note when a burst write reaches a protected block address, it continues the address increment into the protected space but does not write any data to the protected memory. if the address roll over takes the burst write to unprotected space, it resumes writes. the same operation is true if a burst write is initiated within a write protected block. table 6. write protection operation wpen wp wen protected blocks unprotected blocks status register x x 0 protected protected protected 0 x 1 protected writable writable 1 low 1 protected writable protected 1 high 1 protected writable writable figure 11. read instruction timing ~ ~ cs sck so 012345 67 0 765432 1 20212223012345 67 msb lsb data si ~ ~ op-code 0000001 0000 0 0 1 0 a16 a3 a1a2 a0 17-bit address msb lsb d0 d1 d2 d3 d4d5d6d7 not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 13 of 27 nvsram special instructions cy14b101q1/cy14b101q2/cy14b101q3 provides four special instructions, which enables access to the nvsram specific functions: store, recall, asdisb, and asenb. ta b l e 7 lists these instructions. software store (store) instruction when a store instruction is executed, nvsram performs a software store operation. the store operation is performed figure 12. burst mode read instruction timing cs sck so lsb si op-code 17-bit address msb lsb ~ ~ ~ ~ ~ ~ 01 2 3 456 7 0 765432 1 20 21 22 23 01234567 01234567 ~ ~ 0 7 0000 00 11 0 0 00 00 0 a16 a3 a2 a1 a0 d0 d1 d2d3 d4d5d6d7 data byte 1 data byte n msb lsb msb d0 d1 d2d3 d4d5d6d7 d0d7 figure 13. write instruction timing ~ ~ cs sck so 01234 5 6 7 0 765432 1 2021222301234567 msb lsb data d0d1 d2 d3 d4 d5d6d7 si ~ ~ op-code 00 00001 000 0 0 0 0 0 a16 a3 a1a2 a0 17-bit address msb lsb hi-z figure 14. burst mode write instruction timing ~ ~ cs sck so msb lsb si op-code 17-bit address msb lsb ~ ~ ~ ~ 01 234567 0 76 5 432 1 20 21 22 23 01 234567 01 234567 ~ ~ 0 7 0 00000 100000000 a16 a3 a2 a1 a0 hi-z data byte 1 data byte n d0 d1 d2d3 d4d5d6d7 d0 d1 d2d3 d4d5d6d7 d0d7 table 7. nvsram special instructions function name opcode operation store 0011 1100 software store recall 0110 0000 software recall asenb 0101 1001 autostore enable asdisb 0001 1001 autostore disable not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 14 of 27 irrespective of whether a write has taken place since the last store or recall operation. to issue this instruction, the device must be write enabled (wen bit = ?1?). the instruction is performed by transmitting the store opcode on the si pin foll owing the falling edge of cs . the wen bit is cleared on the positive edge of cs following the store instruction. software recall (recall) instruction when a recall instruction is executed, nvsram performs a software recall operation. to issue this instruction, the device must be write enabled (wen = ?1?). the instruction is performed by transmitting the recall opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the recall instruction. autostore enable (asenb) instruction the autostore enable instruction enables the autostore on cy14b101q1. this setting is not nonvolatile and needs to be followed by a store sequence if this is desired to survive the power cycle. to issue this instruction, the device must be write enabled (wen = ?1?). the instruction is pe rformed by transmitting the asenb opcode on the si pin foll owing the falling edge of cs . the wen bit is cleared on the positive edge of cs following the asenb instruction. note if asdisb and asenb instru ctions are executed in cy14b101q1, the device is busy for the duration of software sequence processing time (t ss ). however, asdisb and asenb instructions have no effect on cy14b101q1 as autostore is internally disabled. autostore disable (asdisb) instruction autostore is enabled by def ault in cy14b 101q2/cy14b101q3. the asdisb instruction disables the autostore. this setting is not nonvolatile and needs to be followed by a store sequence if this is desired to survive the power cycle. to issue this instruction, the de vice must be wr ite enabled (wen = ?1?). the instruction is performed by transmitting the asdisb opcode on the si pin following the falling edge of cs . the wen bit is cleared on the positive edge of cs following the asdisb instruction. hold pin operation the hold pin is used to pause the serial communication. when the device is selected and a serial sequence is underway, hold is used to pause the serial communication with the master device without resetting the ongoing serial sequence. to pause, the hold pin must be brought low when the sck pin is low. cs pin must remain low along with hold pin to pause serial communication. while the device serial communication is paused, inputs to the si pin are ignored and the so pin is in the high impedance state. to resume serial communication, the hold pin must be brought high when the sck pin is low (sck may toggle during hold ). figure 15. software store operation figure 16. software recall operation 0 0 1 1 1 1 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 1 1 0 0 0 0 0 cs sck si 0 1 2 3 4 5 6 7 so hi-z figure 17. autostore enable operation figure 18. autostore disable operation figure 19. hold operation 0 1 0 1 1 0 0 1 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 cs sck si so hi-z 0 1 2 3 4 5 6 7 ~ ~ cs sck hold so not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 15 of 27 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ?c maximum accumulated storage time at 150 ? c ambient temperature ...................... 1000 h at 85 ? c ambient temperature .................... 20 years maximum junction temperature ................................. 150 ?c supply voltage on v cc relative to v ss .........?0.5 v to +4.1 v dc voltage applied to outputs in high z state .................................... ?0.5 v to v cc + 0.5 v input voltage ....................................... ?0.5 v to v cc + 0.5 v transient voltage (<20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ........ ............................ ..... +260 ?c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [4] max unit v cc power supply voltage 2.7 3.0 3.6 v i cc1 average v cc current at f sck = 40 mhz. values obtained without output loads (i out = 0 ma) ??10ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store ??10m a i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??5m a i sb v cc standby current cs > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. ??5ma i ix [5] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 ? +1 a input leakage current (for hsb )v cc = max, v ss < v in < v cc ?100 ? +1 a i oz off state output leakage current v cc = max, v ss < v out < v cc ?1 ? +1 a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v v cap [6] storage capacitor between v cap pin and v ss 61 68 180 f v vcap [7, 8] maximum voltage driven on v cap pin by the device v cc = max ? ? v cc v notes 4. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 5. the hsb pin has i out = -2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. 6. min v cap value guarantees that there is a sufficient charge avail able to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. see application note an43593 for more details on v cap options. 7. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage. 8. these parameters are guaranteed by design and are not tested. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 16 of 27 ac test conditions input pulse levels ...................................................0 v to 3 v input rise and fall times (10%?90%) ............................ < 3 ns input and output timing reference levels ....................... 1.5 v data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 6pf c out output pin capacitance 8pf thermal resistance parameter [9] description test conditions 16-pin soic 8-pin dfn unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 55.17 17.7 ?c/w ? jc thermal resistance (junction to case) 2.64 18.8 ?c/w ac test loads and waveforms figure 20. ac test loads and waveforms 3.0 v output 5 pf r1 r2 789 ? 3.0 v output 30 pf r1 r2 789 ? 577 ? 577 ? note 9. these parameters are guaranteed by design and are not tested. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 17 of 27 ac switching characteristics over the operating range [10] cypress parameter alt. parameter description 40 mhz unit min max f sck f sck clock frequency, sck ? 40 mhz t cl t wl clock pulse width low 11 ? ns t ch t wh clock pulse width high 11 ? ns t cs t ce cs high time 20 ? ns t css t ces cs setup time 10 ? ns t csh t ceh cs hold time 10 ? ns t sd t su data in setup time 5 ? ns t hd t h data in hold time 5 ? ns t hh t hd hold hold time 5 ? ns t sh t cd hold setup time 5 ? ns t co t v output valid ? 9 ns t hhz [11] t hz hold to output high z ? 15 ns t hlz [11] t lz hold to output low z ? 15 ns t oh t ho output hold time 0 ? ns t hzcs t dis output disable time ? 25 ns switching waveforms figure 21. synchronous data timing (mode 0) figure 22. hold timing hi-z valid in hi-z cs sck si so t cl t ch t css t sd t hd t co t oh t cs t csh t hzcs valid in valid in cs sck hold so t sh t hhz t hlz t hh t sh t hh ~ ~ notes 10. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh and load capacitance shown in figure 20 . 11. these parameters are guaranteed by design and are not tested. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 18 of 27 autostore or power-up recall over the operating range parameter description cy14b101q1/cy14b101q2/ cy14b101q3 unit min max t fa [12] power-up recall duration ? 20 ms t store [13] store cycle duration ? 8 ms t delay [14] time allowed to complete sram cycle ? 25 ns v switch low voltage trigger level ? 2.65 v t vccrise [15] v cc rise time 150 ? ? s v hdis [15] hsb output disable voltage ? 1.9 v t lzhsb [15] hsb high to nvsram active time ? 5 ? s t hhhd [15] hsb high active time ? 500 ns switching waveforms figure 23. autostor e or power-up recall [16] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t fa t fa hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 13 13 17 17 notes 12. t fa starts from the time v cc rises above v switch. 13. if an sram write has not taken place since the last nonvol atile cycle, autostore or hardware store is not initiated. 14. on a hardware store, software store / recall, autostore enable / disable and autostore initiation, sram operation continues to be enabled for time t delay . 15. these parameters are guaranteed by design and are not tested. 16. read and write cycles are ignored during store, recall, and while v cc is below v switch. 17. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 19 of 27 software controlled store and recall cycles over the operating range parameter description cy14b101q1/cy14b101q2/ cy14b101q3 unit min max t recall recall duration ? 200 ? s t ss [18, 19] soft sequence processing time ? 100 ? s switching waveforms figure 24. software store cycle [19] figure 25. software recall cycle [19] figure 26. autostore enable cycle figure 27. autostore disable cycle 0 0 1 1 1 1 0 0 cs sck si rwi hi-z 0 1 2 3 4 5 6 7 rdy t store 0 1 1 0 0 0 0 0 cs sck si 0 1 2 3 4 5 6 7 rwi hi-z rdy t recall 0 1 0 1 1 0 0 1 cs sck si 0 1 2 3 4 5 6 7 rwi hi-z rdy t ss 0 0 0 1 1 0 0 1 sck si 0 1 2 3 4 5 6 7 rwi hi-z rdy cs t ss notes 18. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 19. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 20 of 27 hardware store cycle over the operating range parameter description cy14b101q3 unit min max t phsb hardware store pulse width 15 ? ns switching waveforms figure 28. hardware store cycle [20] ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k: resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set ~ ~ ~ ~ ~ ~ note 20. if an sram write has not taken place since the last nonvol atile cycle, no autostore or hardware store takes place. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 21 of 27 ordering code definitions ordering information ordering code package diagram package type operating range CY14B101Q2-LHXI 001-50671 8-pin dfn (with v cap ) industrial all the above parts are pb-free. option: t - tape and reel blank - std. q - serial spi nvsram density: 101 - 1 mb voltage: b - 3.0 v cypress cy 14 b 101 q 2-sf x i t 14 - nvsram pb-free package: sf - 16 soic lh - 8 dfn 1 - with wp 2 - with v cap 3 - with v cap, wp and hsb temperature: i - industrial (?40 to 85 c) not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 22 of 27 package diagrams figure 29. 8-pin dfn (5 6 0.85 mm) package outline, 001-50671 1. all dimensions are in millimeters 3. based on ref jedec # mo- 240 except dimensions (l) and (b) notes: 2. package weight: tbd 001-50671 *c not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 23 of 27 figure 30. 16-pin soic (0.413 0.2 99 0.0932 inches) package outline, 51-85022 package diagrams (continued) 51-85022 *e not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 24 of 27 acronyms document conventions units of measure acronym description cpha clock phase cpol clock polarity dfn dual flat no-lead eeprom electrically erasable programmable read-only memory eia electronic industries alliance i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit nvsram non-volatile static random access memory rwi read and write inhibit rohs restriction of hazardous substances spi serial peripheral interface sonos silicon-oxide-nitride-oxide semiconductor soic small outline integrated circuit sram static random access memory symbol unit of measure c degree celsius hz hertz khz kilohertz k? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 25 of 27 document history page document title: cy14b101q1/cy 14b101q2/cy14b101q3, 1-mbit (128 k 8) serial spi nvsram document number: 001-50091 rev. ecn orig. of change submission date description of change ** 2607408 gsin / gvch / aesa 12/19/08 new data sheet. *a 2654487 gvch / pyrs 02/04/2009 moved from advance information to preliminary changed part number from cy14b101qxa to cy14b101qx updated pin description of v cap pin updated device operation and spi peripheral interface description added factory setting values for bp1, bp2 and wpen bits updated real time clock operation description changed i cc2 from 5ma to 10ma *b 2733293 gvch / aesa 07/08/2009 corrected typo error in the document history page (description of change) corrected typo error of footnote 2 and 3 updated autostore operation description updated test condition of i cc1 and i sb parameter updated v hdis parameter description *c 2757348 gvch 08/28/2009 moved data sheet status from preliminary to final removed commercial temperature related specs added thermal resistance values for 16-soic and dfn package added note to write sequence (write) description *d 2839453 gvch / pyrs 01/06/10 changed store cycles to quan tumtrap from 200k to 1 million updated figure 3 added contents *e 2894833 gvch 03/17/10 removed inactive parts from the ordering information table. updated links in sales, solutions, and legal information . updated package diagrams . *f 2910569 btk / gvch 04/12/10 updated figure 1 to show the pad in the pin diagrams. updated table 1 to give information on the pad. updated power-down description power-on reset : added status of bits 4-6 table 4 : added definition of bits 4-6 updated figure 21 , figure 22 , and figure 23 updated footnote 11 removed t dhsb parameter updated figure 28 *g 3037045 gvch 10/09/10 changed ground naming convention from gnd to v ss updated power-down description power-on reset : added status of bits 4-6 table 4 : added definition of bits 4-6 updated figure 8 updated hold pin operation , figure 19 and figure 22 to indicate that cs pin must remain low along with hold pin to pause serial communication added figure 26 and figure 27 added acronyms and units of measure table *h 3134300 gvch 01/11/11 hardware store and hsb pin operation : added more clarity on hsb pin operation updated t lzhsb parameter description *i 3320877 gvch 07/19/11 added footnote 6 and 10. *j 3493427 gvch 01/13/2012 updated package diagrams . no technical updates. not recommended for new designs
cy14b101q1 cy14b101q2 cy14b101q3 document number: 001-50091 rev. *l page 26 of 27 *k 3665165 gvch 08/03/2012 updated maximum ratings (changed ?ambient temperature with power applied? to ?maximum junction temperature?). updated dc electrical characteristics (added v vcap parameter and its details, added note 7 and referred the same note in v vcap parameter, also referred note 8 in v vcap parameter). *l 4010138 gvch 05/24/2013 updated package diagrams : spec 51-85022 ? changed revision from *d to *e. added watermark as ?not recommended for new designs.? document history page (continued) document title: cy14b101q1/cy 14b101q2/cy14b101q3, 1-mbit (128 k 8) serial spi nvsram document number: 001-50091 rev. ecn orig. of change submission date description of change not recommended for new designs
document number: 001-50091 rev. *l revised may 24, 2013 page 27 of 27 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14b101q1 cy14b101q2 cy14b101q3 ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 not recommended for new designs

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